Clocked dynamic CMOS circuits typically have both a pre-charge and an evaluate phase during a cycle. Static CMOS circuits, on the other hand, evaluate and then hold the state until the next cycle. Each of these circuit families has its own advantages and disadvantages. Dynamic circuits are fast, but they are also susceptible to noise. Static circuits are slower than dynamic circuits, but they have greater noise immunity. It would be desirable to combine the benefits of these different circuit families without also incorporating their disadvantages.
Typically, a static CMOS circuit is slower than a dynamic circuit for several reasons:
1) The delay of static CMOS circuits has history dependence based on the input patterns from the previous cycle; PA1 2) Static CMOS circuits can switch multiple times within a cycle. For example, in the case of a two-way NOR, if the first input switches from 1 to 0 and later the second input switches from 0 to 1, then the output will switch from one 0 to 1 to 0. The delay through the NOR is valid only after the second input has switched; PA1 3) Static CMOS has twice the gate capacitance to drive since it drives both p-channel and n-channel devices on the next stage. Dynamic circuits, on the other hand, have half the load of static CMOS since they drive only n-channel devices.
Combining the best aspects of dynamic and static circuits, we have developed a new circuit set which is faster than static circuits and has better noise immunity than dynamic circuits.